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Guild: wafer.space Community
Channel: 📐 - Designing / 🕰️-analog
After: 2026-04-30 11:59 p.m.
Before: 2026-06-01 12:00 a.m.
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[2026-05-06 3:17 a.m.] tishamdhar
I am interested in designing a metering ASIC for energy. Design block suggestions and toolchains welcome. Looking to use Tiny Tapeout or Wafer Space given space required.


[2026-05-11 9:46 p.m.] polyfractal
world's least optimized pixel array 😂

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[2026-05-11 11:26 p.m.] namibj
Are you doing photoelectronics for Run2/3?


[2026-05-11 11:27 p.m.] namibj
(also that's why back illumination and what microlenses are for)


[2026-05-12 12:36 a.m.] polyfractal
If I can get a bit more of it done in the next week or two, yep! Would love to tape this out for Run2.  it's an "event pixel" design, where each pixel fires asynchronously when its threshold is breached. They register changes in a scene rather than a clocked frame


[2026-05-12 12:50 a.m.] namibj
ahhhhh.
I was about to say, at that lack of density, might almost go for SPAD (but the DRCs likely prevent the necessary field-smoothing rounding).


[2026-05-12 1:32 a.m.] polyfractal
I should be able to get density higher, ALIGN freaked out once I added the photodiode into the circuit. Either needs some tweaks, or just pull the diode out and hand-place them. but otoh 32x32 is plenty for demonstration and it'll probably make the rest of the project easier so 🤷‍♂️ 🙂


[2026-05-12 1:33 a.m.] polyfractal
SPADs would be neat though!


[2026-05-12 1:34 a.m.] polyfractal
think I saw a paper somewhere with a SPAD done in skywater 130? or maybe even GF 180? will try to find it


[2026-05-12 2:39 a.m.] namibj
I'm just a little sad that silicon's indirect bandgap means you can't just use a photodiode for bidirectional communications like you can with e.g. a 405nm-pumped COTS blue LED (load modulation in photovoltaic biasing severely varies how much shunt current in the diode produces electroluminescence; this is fairly easy to separate at the end with the 405nm source and can be used as a back-channel there).
Unless you happen to know some clever trick that'd allow one to do vertical surface emitting data back channel from on top of a gf180mcuD die to some "beefier" system. I mean I guess tbf things like osram/ams's `PLPVYL1 940A_E` 20~60ct/each (depending on quantity) VCSEL do exist... (wish there was a SPICE for it, or even just capacitance information, but oh well....)


[2026-05-12 2:41 a.m.] namibj
ohhh, it even hits nicely into peak Si photodiode A/W efficiency....


[2026-05-12 4:57 a.m.] polyfractal
could abuse resistive elements or even just big gates and emit IR 😅  

I think porous silicon can be used to make an LED without any other materials, but it's a pretty crapp LED iirc (and far red)


[2026-05-12 5:00 a.m.] namibj
tho apparently you can just buy VCSEL for so cheap if you buy ones marketed to lower power IR illumination; I should get one next time and try to measure capacitance.


[2026-05-14 8:09 p.m.] nmz787
AnalogCoder: Analog Circuit Design via Training-Free Code Generation
https://arxiv.org/pdf/2405.14918

LADAC: Large Language Model-driven Auto-Designer for Analog Circuits
https://www.techrxiv.org/doi/full/10.36227/techrxiv.170473941.10097233/v1


Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System
https://par.nsf.gov/servlets/purl/10356326


[2026-05-14 8:09 p.m.] nmz787
@BreakingTaps  ^


[2026-05-14 8:09 p.m.] nmz787
ever come across them?


[2026-05-14 8:11 p.m.] polyfractal
I've seen MAGICAL before! MAGICAL and ALIGN were both funded by the same DARPA program and were sort of sibling projects. After looking over them, it seemed that MAGICAL is abandoned/not-very-active and looked harder to extend to other PDKs (the paper or project had a note about how it was difficult to port).

Dunno about the other two, will take a look!


[2026-05-18 6:47 p.m.] mithro_
Stupid idea, but could the metal layers be used as reflectors and/or diffraction gratings/etc ?


[2026-05-18 6:48 p.m.] namibj
sure, kinda static tho


[2026-05-18 6:48 p.m.] namibj
and I at least don't know how good the absolute scale tolerance of the litho is


[2026-05-18 7:10 p.m.] polyfractal
I was actually looking into using the metal lines as gratings / structural color recently. Unfortunately the min pitch is pretty large. M1 could get you some mid-visible color, but M2+ is all pretty far red. 🙁 

I wonder if you could throw a resistive element under a metal reflector layer and use the thermal expansion though? be sort of like a deformable mirror but fully monolithic 🤔


[2026-05-18 7:11 p.m.] namibj
Just don't do what tholin seems to have accidentally done (crack dies after first power cycle)

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[2026-05-18 7:11 p.m.] mithro_
That is why you get 1,000 of them 😉


[2026-05-18 7:12 p.m.] mithro_
Could you use some type of pattern between the layers or something?


[2026-05-18 7:13 p.m.] namibj
I'd guess the silicon could be modulated in transparency via presence of minority carriers, for some wavelength at least?


[2026-05-18 7:13 p.m.] polyfractal
quite possibly! afraid that's approaching the end of my photonics knowledge. probably easy enough to simulate though


[2026-05-18 7:14 p.m.] mithro_
The simulation itself might be an interesting video? 😛


[2026-05-18 7:23 p.m.] namibj
ahhh yeah internet says _Free-Carrier Plasma Dispersion Effect_


[2026-05-18 7:24 p.m.] namibj
modulate refractive index usable on 1310/1550 nm light in silicon photonics waveguides.


[2026-05-18 7:25 p.m.] namibj
just have a pn/pin junction and either reverse bias the former to desired width of depletion zone or forward bias the latter to desired minority carrier density


[2026-05-18 7:36 p.m.] namibj
as silicon should be pretty transparent there normally, it might work having it be in the resonator and to use it to minutely shift the resonance peak to doa  little FM modulation


[2026-05-18 8:37 p.m.] polyfractal
heh ran some numbers on this, _very roughly_ you could get 5-10nm of vertical displacement so 10-20nm of reflected displacement. Not nothing!


[2026-05-18 8:41 p.m.] namibj
consider comparing to carrier density effects in vertical transmission perhaps for the iirc fairly accessible 1310nm


[2026-05-19 4:13 p.m.] mattvenn
or use multiple metal layers with offsets?


[2026-05-20 12:02 p.m.] tholin
Muuuuch better!

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[2026-05-20 12:04 p.m.] tholin
And can still drive a 1K load


[2026-05-20 12:05 p.m.] tholin
Yes, I could still make it use less current by optimizing it to drive smaller loads, but this is a nice tradeoff


[2026-05-20 12:05 p.m.] tholin
My next chip is only going to have 2 of these anyways


[2026-05-21 1:26 a.m.] mithro_
@Tholin - Invest in power gating anyway 😛

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[2026-05-23 10:04 p.m.] polyfractal
Welp, defeated by DRC again 🙃  

working on a 1T pixel design based off of this paper (https://www.mdpi.com/1424-8220/9/1/131). Needs a floating P body which I figured you could build with DNWell -> LVPWell -> NPlus. Got everything dialed into minimum size that would make DRC happy, then arrayed it and discovered another DRC rule: LVPWell to LVPWell must be >1.4um. There goes my pixel density! 😂  

Should still work, but I was hoping for <2-3um pitch so I could play with sub-diffraction limit oversampling stuff. But with that DRC limitation might as well make the active area larger and run it as a normal detector.

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[2026-05-23 10:07 p.m.] polyfractal
better screenshot

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[2026-05-24 1:51 a.m.] namibj
Can't you use pmos devices instead and not need the dnwell?
Also I still don't quite get where and how STI is litho'd. Like, what patterns/shapes even do that?

Also, https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_04.html says:
> Equi potential min space  0.86V

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[2026-05-24 1:56 a.m.] namibj
Also maybe look at https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_07.html it feels like you may be doing things similar to those restrictions depending on biasing conditions?

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[2026-05-24 2:51 p.m.] polyfractal
Hmm I'll need to double check, but I don't think a normal pmos device would give the floating p-body that's needed. It'd be an nwell in the psub, and then p+ contacts


[2026-05-24 2:52 p.m.] polyfractal
need to look into that equipotential thing, not sure how it's calculated. Would be great to use that spacing! I think because all the floating p-body sections are isolated, they are considered at different potentials by the DRC? not sure


[2026-05-24 3:42 p.m.] namibj
No I mean like, the photodiode works regardless of whether it's illuminated from the P-side or the N-side, right?
Voltages flip, sure, but I'd not think you'd need particularly high performance transistor channels in those pixels so that's not on it's own at least reason to go for N-channel device.


[2026-05-24 3:48 p.m.] namibj
Well I'm pretty sure it's (only) a latchup concern; I'd guess this might cause charge-spillover to adjacent cells similar in visual effect to what we remember from old CCD digital cameras.

Xyce has 2D TCAD on hand you could use to model the latchup behavior.
I guess the biggest hurdle would be that it's potentially gonna blow the 4-electrode limit in their code.

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[2026-05-24 3:50 p.m.] polyfractal
Ah I misunderstood. Yes, N or P is fine, although P is preferred because hole accumulation is (apparently) better for imaging. less noisy I think?

But the main thing is that it needs a floating/isolated body of the diode. Light passes through the poly gate, creates electron/hole pairs, the electrons are swept away to drain and the holes remain which then alters the IV curve of the transistor when it is read out. That's how they get a "3T" pixel with one transistor, it acts as integration, readout and reset all in one. But needs the floating/isolated body to do it


[2026-05-24 3:50 p.m.] namibj
1 source, 2 gate, 3 drain, 4 substrate, (maybe 5 next_drain), 5 next_gate, 6 next_source


[2026-05-24 3:51 p.m.] polyfractal
I was a little confused why it was codified in DRC, it seems like a functional problem but not really a design rule / layout issue 🙁


[2026-05-24 3:57 p.m.] namibj
> One should notice that in readout mode, some stored holes are displaced under the source due to shrink of charge storage region under the gate and source potential lowering. This shift of the charge storage region to the source and toward the pixel edge should be stopped to avoid electrical crosstalk. One solution to the problem is to employ STI (shallow trench isolation), as shown in Figure 2. It was adopted in our first design configuration.
Yeah I for one don't quite get where the electrodes are in Fig.2 🙁

Have you considered asking those researchers?


[2026-05-24 3:58 p.m.] namibj
Me when I look at one too many sky130 DRC's again and go _huh...._

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[2026-05-24 3:59 p.m.] namibj
[insert villager sound effect]


[2026-05-24 3:59 p.m.] polyfractal
might give them a ping! can't hurt


[2026-05-24 3:59 p.m.] namibj
worst case they don't answer


[2026-05-24 4:00 p.m.] namibj
well, worst worst case they snipe your slot on Run2 😄


[2026-05-25 12:07 a.m.] nmz787
At work we definitely have some DRs that are just for electrical "dummyproofing", and since my team draws mechanical and litho designs, we often get waivers for some of those rules


[2026-05-25 12:08 a.m.] nmz787
However we also can ask the process integration owners and ask questions like "how does the STI actually get patterned" if we're confused or just curious


[2026-05-25 12:09 a.m.] nmz787
I need that GDS3D isometric view


[2026-05-25 12:09 a.m.] nmz787
After 5 years drawing OASIS/GDS... I still get confused over all these layers on top of layers


[2026-05-25 12:10 a.m.] namibj
same sadly KLayout PDK only has that for sky130A (and maybe ihp I don't know), not gf180mcuD 🙁


[2026-05-25 12:10 a.m.] nmz787
It's easy (ish) to make a layerstack


[2026-05-25 12:12 a.m.] nmz787
I should really publish my layerstack generator helper... basically just a CLI that takes the list of layers, already arranged in order in a text file, and asks you what Z and how thick you want it... And accumulates your overall height to the next Z default entry (in case you have two layers at the same Z, like the diffusions)


[2026-05-25 12:13 a.m.] nmz787
Although I'm sure pointing AI at the existing gds3d layerstacks as examples and asking it to generate the helper I just said, would do it in one or two prompts


[2026-05-25 12:14 a.m.] nmz787
I believe I already have a gf180 prop file for gds3d, but am not on my PC right now


[2026-05-25 12:17 a.m.] namibj
feed it the https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html and https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html

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[2026-05-25 12:22 a.m.] nmz787
Need the dl;dt too, I think there's a layermap for klayout that I'd start with, but those images would be good to finish the details!


[2026-05-25 12:22 a.m.] namibj
Sure


[2026-05-26 9:47 a.m.] 246tnt
https://discord.com/channels/1009193568256135208/1015911926053740544/1508755468275814470


[2026-05-26 9:47 a.m.] 246tnt
TT will be running an experimental slot in run2 for analog designs. See above for details.


[2026-05-26 1:33 p.m.] mithro_
KLayout has some type of cross-sectioning mode - https://klayoutmatthias.github.io/xsection/

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https://klayoutmatthias.github.io/xsection/
XSection Project Home Page
Former xsection@klayout project


[2026-05-26 8:12 p.m.] namibj
https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_05.html

I think I'm doing everything right, taking a `nmos_06v6_nvt` PCell that I confirm next to the DUT extracts just fine through magic, and _deleting just the dualgate layer rectangle_ on the DUT copy of the (all flattened) PCell structure, but magic doesn't spell complaints and the DUT just won't spawn in the extracted SPICE?
I also have a tiny `nmos_03v3` and I just confirmed that deleting also the NAT box on the DUT makes it extract as the plain `nmos_03v3` it's then expected to extract as.

Do we or do we not have those available at the GDS level? 

I can understand (with much unhappyness) if there's no design support (LVS, other extraction, spice, xschem, etc.), but otherwise I'd quite very like to know where I would have been supposed to read about us explicitly not having `nmos_03v3_nvt`.


[2026-05-26 8:49 p.m.] bailey8889
Maybe `grep _nvt $PDK_ROOT/gf180mcu/libs.tech/ngspice/*`


[2026-05-26 9:01 p.m.] 246tnt
I guess you can tape one out and measure it and see if it actually works.


[2026-05-26 9:03 p.m.] namibj
That's my fallback.


[2026-05-26 11:59 p.m.] mithro_
I *believe* the GDSFactory people are hoping to do some test circuits to do some verification circuits.


[2026-05-27 12:01 a.m.] namibj
@Thomas Pluck 2.1 `nfet_03v3_nvt` misses models and currently even extraction; it's only implied from some DRCs to exist. Etest if any of that happens would be _awesome_ to capture.


[2026-05-27 10:26 a.m.] namibj
Oh and if anyone etests that one, don't only do L=1.8, go down towards the L=0.28.


[2026-05-27 2:32 p.m.] mole99
Started a thread.


[2026-05-27 4:14 p.m.] tpluck_
Plan was that we can generate test structures on a left over Run 2 half slot right?


[2026-05-27 4:17 p.m.] tpluck_
No sense wasting a creative TT slot on device characterization.


[2026-05-27 8:06 p.m.] mithro_
Correct!


[2026-05-30 12:32 a.m.] mithro_
@BreakingTaps - You might find https://docs.google.com/presentation/d/e/2PACX-1vS2jJzvahcR7M6YPl6omPSDk7ZW6sFhqpsh4mxRzwc5JhHkUPudI62qpevA1WWu2g/pub?start=false&loop=false&delayms=3000 interesting.

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https://docs.google.com/presentation/d/e/2PACX-1vS2jJzvahcR7M6YPl6omPSDk7ZW6sFhqpsh4mxRzwc5JhHkUPudI62qpevA1WWu2g/pub?start=false&loop=false&delayms=3000
[Chipathon 2026 4th Weekly -  29 May 2026] - Track D.pptx
IEEE-SSCS Chipathon 2026 Track D: AI/LLM-assisted circuits gLayout Design Walkthrough Presented by: Anhang Li (anhangli@umich.edu) Track Leads: Mehdi Saligane, Saptarshi Ghosh, Osama Khan, Trio Adiono/Nur, Mauricio Montanares, Muhammed Luqman Jukaku, Luighi Viton 1


[2026-05-30 3:41 a.m.] anfroholic
That's a private repo


[2026-05-30 5:58 a.m.] mithro_
I think that fixes it?


[2026-05-30 5:59 a.m.] anfroholic
Yes, fixed


[2026-05-30 5:46 p.m.] polyfractal
ooh neat, thanks for the ping!


[2026-05-30 6:59 p.m.] namibj
Oh yes thanks for the link.
If anyone has a link to how that LLM assitance there happens to be practically usable, I'd appreciate to see if it appers to be effective for my MCML efforts that way.


[2026-05-31 8:49 p.m.] 246tnt
I need a quick&dirty current reference. Nominal would be 30 uA at 3.3V but should be usable at 5V and acceptable range would be 20~60 uA. Anyone got something easy to propose ? 😅


[2026-05-31 10:05 p.m.] dorythecat_v2


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[2026-05-31 10:06 p.m.] dorythecat_v2
ive used this circuit before and on a punch it's good enough


[2026-05-31 10:06 p.m.] dorythecat_v2
otherwise, a high enough voltage and a high enough resistor should work


[2026-05-31 10:07 p.m.] 246tnt
I meant an on-chip reference ... you can't make zener in gf180mcu


[2026-05-31 11:05 p.m.] tdextrous
Started a thread.


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